Joint Optimization of Low-power DCT Architecture and Effcient Quantization Technique for Embedded Image Compression

International audienceThe Discrete Cosine Transform (DCT)-based image com- pression is widely used in today's communication systems. Signi cant research devoted to this domain has demonstrated that the optical com- pression methods can o er a higher speed but su er from bad image quality and a growing complexity. To meet the challenges of higher im- age quality and high speed processing, in this chapter, we present a joint system for DCT-based image compression by combining a VLSI archi- tecture of the DCT algorithm and an e cient quantization technique. Our approach is, rstly, based on a new granularity method in order to take advantage of the adjacent pixel correlation of the input blocks and to improve the visual quality of the reconstructed image. Second, a new architecture based on the Canonical Signed Digit and a novel Common Subexpression Elimination technique is proposed to replace the constant multipliers. Finally, a recon gurable quantization method is presented to e ectively save the computational complexity. Experimental results obtained with a prototype based on FPGA implementation and com- parisons with existing works corroborate the validity of the proposed optimizations in terms of power reduction, speed increase, silicon area saving and PSNR improvement

Etude, Modélisation et Amélioration des Performances desConvertisseurs Analogique Numérique Entrelacés dans le Temps

Dans un contexte où les systèmes communicants fleurissent, les Convertisseurs Analogique Numérique CAN doivent suivre les demandes des nouveaux standards de télécommunications. Un convertisseur seul, ne peut pas allier rapidité, précision et faible consommation de puissance. Dans le cadre de nos travaux, nous somme intéressé à une structure prometteuse de CAN basée sur l'entrelacement temporel de plusieurs convertisseurs, TIADC. Le taux d'échantillonnage augmente proportionnellement avec le nombre de CAN mais des problèmes de disparité entre les différents CAN réduisent la résolution effective du TIADC. Dans ce mémoire, nous avons contribuer à l'étude de ces convertisseurs, notamment aux pertes engendrées par les disparités entre les différents convertisseurs. La structure du TIADC a été modélisé dans un environnement de description matérielle. Plusieurs solutions de calibrations existantes ont été simulé afin de vérifier leur fonctionnement et de pouvoir proposer deux méthodes de correction. Une première méthode en différé visant le domaine de l'instrumentation et une seconde, en ligne visant des application de élécommunications. La première méthode a été vérifié par des données expérimentales, la seconde était implémenté dans un FPGA et vérifié par des tests et des mesures

A VLSI implementation of a new simultaneous images compression and encryption method

International audienceIn this manuscript, we describe a fully pipelined single chip architecture for implementing a new simultaneous image compression and encryption method suitable for real-time applications. The proposed method exploits the DCT properties to achieve the compression and the encryption simultaneously. First, to realize the compression, 8-point DCT applied to several images are done. Second, contrary to traditional compression algorithms, only some special points of DCT outputs are multiplexed. For the encryption process, a random number is generated and added to some specific DCT coefficients. On the other hand, to enhance the material implementation of the proposed method, a special attention is given to the DCT algorithm. In fact, a new way to realize the compression based on DCT algorithm and to reduce, at the same time, the material requirements of the compression process is presented. Simulation results show a compression ratio higher than 65% and a PSNR about 28 dB. The proposed architecture can be implemented in FPGA to yield a throughput of 206 MS/s which allows the processing of more than 30 frames per second for 1024x1024 images

Implementation techniques of high-order FFT into low-cost FPGA

International audienceIn this paper, our objective is to detail know-how and techniques that can help the designer of electronic circuits to develop and to optimize their own IP in a reasonable time. For this reason, we propose to optimize existing FFT algorithms for low-cost FPGA implementations. For that, we have used short length structures to obtain higher length transforms. Indeed, we can obtain a VLSI structure by using log4 (N) 4-point FFTs to construct N-point FFT rather than (N/8) log8 (N) 8-point FFTs. Furthermore, two techniques are used to yield with VLSI architecture. Firstly, the radix-4 FFT is modified to process one sample per clock cycle. Secondly, the memory is shared and divided into 4 parts to reduce the consumed resources and to improve the overall latency. Comparisons with commercial IP cores show that the low area architecture presents the best compromise in terms of speed/are

A subband FFT-based method for static errors compensation in Time-Interleaved ADCs

Invited paperInternational audienceTime-interleaving several Analog to Digital Converters (ADC) is considered as efficient solution to significantly increase the sampling rate. Unfortunately, due to the manufacturing process, static errors in Time-Interleaved Analog to Digital Converter (TIADC) often generate undesirable spurs which reduce the TIADC effective resolution. In this paper we propose a new blind and online digital calibration method for offset and gain mismatch based on subband FFT decomposition technique. Numerical simulations and some implementation issues are used to show the efficiency of the proposed calibration architecture

Etude, Modélisation et Amélioration des Performances des<br />Convertisseurs Analogique Numérique Entrelacés dans le Temps

To comply with new telecommunication standard requirements, Analog to Digital ConverterADC should provide high sample rate, high resolution and low power consumption. With today's technologies, only one converter cannot achieve these requirements. To cope with this problem, one solution consists in parallelizing existing ADC cores on a die to increase the sampling rate for the same resolution and power consumption. The resulting system is called Time Interleaved Analog to Digital Converter TIADC. However, TIADC systems introduce new set of problem : indeed, each converter is characterized by its proper errors, mismatches between ADC cause undesirable spurs. The main thesis contribution is about TIADC spectral parameter loss study caused by mismatches effect, TIADC modelling and material description. A special attention is given to TIADC compensation methods by proposing two solutions : the first one is an offline method used for measurement applications. The second is an online method based on adaptive filtering for telecommunications applications. The first method is verified by experimental data, the second one is implemented into FPGA and verified by tests and measures.Dans un contexte où les systèmes communicants fleurissent, les Convertisseurs Analogique Numérique CAN doivent suivre les demandes des nouveaux standards de télécommunications. Un convertisseur seul, ne peut pas allier rapidité, précision et faible consommation de puissance. Dans le cadre de nos travaux, nous somme intéressé à une structure prometteuse de CAN basée sur l'entrelacement temporel de plusieurs convertisseurs, TIADC. Le taux d'échantillonnage augmente proportionnellement avec le nombre de CAN mais des problèmes de disparité entre les différents CAN réduisent la résolution effective du TIADC. Dans ce mémoire, nous avons contribuer à l'étude de ces convertisseurs, notamment aux pertes engendrées par les disparités entre les différents convertisseurs. La structure du TIADC a été modélisé dans un environnement de description matérielle. Plusieurs solutions de calibrations existantes ont été simulé afin de vérifier leur fonctionnement et de pouvoir proposer deux méthodes de correction. Une première méthode en différé visant le domaine de l'instrumentation et une seconde, en ligne visant des application de élécommunications. La première méthode a été vérifié par des données expérimentales, la seconde était implémenté dans un FPGA et vérifié par des tests et des mesures

A low-power, high-speed DCT architecture for image compression: Principle and implementation

International audienc

A Low-Power, High-Speed DCT architecture for image compression: principle and implementation

International audienc

Joint Optimization of Low-power DCT Architecture and Effcient Quantization Technique for Embedded Image Compression

International audienceThe Discrete Cosine Transform (DCT)-based image com- pression is widely used in today's communication systems. Signi cant research devoted to this domain has demonstrated that the optical com- pression methods can o er a higher speed but su er from bad image quality and a growing complexity. To meet the challenges of higher im- age quality and high speed processing, in this chapter, we present a joint system for DCT-based image compression by combining a VLSI archi- tecture of the DCT algorithm and an e cient quantization technique. Our approach is, rstly, based on a new granularity method in order to take advantage of the adjacent pixel correlation of the input blocks and to improve the visual quality of the reconstructed image. Second, a new architecture based on the Canonical Signed Digit and a novel Common Subexpression Elimination technique is proposed to replace the constant multipliers. Finally, a recon gurable quantization method is presented to e ectively save the computational complexity. Experimental results obtained with a prototype based on FPGA implementation and com- parisons with existing works corroborate the validity of the proposed optimizations in terms of power reduction, speed increase, silicon area saving and PSNR improvement